1. Technical Field
The present invention relates to semiconductor integrated circuit (IC) devices and methods of fabricating the same and, more particularly, to semiconductor IC devices including gate patterns having a step difference therebetween and a connection line interposed between the gate patterns and methods of fabricating the same.
2. Description of the Related Art
Typically, a semiconductor IC device is fabricated by forming gate patterns in a cell array region and a peripheral circuit region into which a semiconductor substrate is divided. In this case, the semiconductor substrate includes active regions and a device isolation layer, which are disposed in the cell array region and the peripheral circuit region. Due to a reduction in the design rule, the semiconductor IC device includes a gate pattern disposed under top surfaces of the active region and the device isolation layer in the cell array region and another gate pattern disposed on a top surface of the active region in the peripheral circuit region. Thus, the gate pattern disposed in the cell array region constitutes a 3-dimensional transistor in the semiconductor IC device. The semiconductor IC device can improve current drivability using the gate pattern disposed in the cell array region compared with before the reduction in the design rule.
However, with continuing reduction in the design rule, the semiconductor IC device may not have gate patterns that improve current drivability. This is due to the fact that the gate patterns disposed in the cell array region and the peripheral circuit region are simultaneously formed under and on the top surface of the active region, respectively, in order to simplify a semiconductor fabrication process. Thus, since the gate patterns have a step difference therebetween relative to the top surface of the active region, the semiconductor fabrication process may attack the gate pattern disposed in the cell array region and/or the gate pattern disposed in the peripheral circuit region according to process circumstances. As a result, the gate pattern disposed in the cell array region and/or the gate pattern disposed in the peripheral circuit region may be attacked and undesirably shaped during the semiconductor fabrication process.
The above-described gate patterns have been disclosed in U.S. Patent Publication No. 2006/0097314 by Hiroyuki Uchiyama. According to U.S. Patent Publication No. 2006/0097314, a semiconductor substrate having a memory cell region and a peripheral circuit region is prepared. An isolated trench is disposed in the memory cell region and the peripheral circuit region. The isolated trench is filled with a silicon oxide layer. The silicon oxide layer defines an active region disposed in the memory cell region and an active region disposed in the peripheral circuit region. Gate electrodes are disposed on the active regions and protrude from top surfaces of the active regions, respectively. The gate electrodes are formed of a conductive material. Caps are disposed on the gate electrodes, respectively. The caps are formed of an insulating material. Contact plugs are disposed adjacent to the gate electrodes and contact the active regions, respectively. The contact plugs are formed of a conductive material.
However, according to U.S. Patent Publication No. 2006/0097314, a semiconductor device may not improve current drivability along with a reduction in the design rule because the gate electrodes disposed in the memory cell region protrude from the top surface of the active region. In other words, with the continual shrinkage of design rules, the gate electrodes may greatly increase parasitic capacitances along with the contact plugs in the memory cell region and the peripheral circuit region. Specifically, the gate electrodes disposed in the memory cell region may have short circuits with the contact plugs on the active regions of the memory cell region due to the continual shrinkage of design rules. As a result, the contact plugs may increase the internal resistances of the gate electrodes in the memory cell region, thereby degrading the current drivability of the semiconductor device. The present invention addresses these and other disadvantages of the conventional art.